1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the present invention relates to a wet processing method of protecting a copper wiring pattern.
2. Description of the Related Art
With the enlargement of a chip size and the miniaturization of a minimum processing dimension, a parasitic capacitance and a wiring line resistance increase to cause a wiring delay. In order to avoid it, an interlayer insulating film with a low dielectric constant is used for decrease of the parasitic capacitance. Also, a copper wiring with a small resistance is used for decrease of the wiring line resistance. Thus, by using the interlayer insulating film with the low dielectric constant for decrease of the capacitance C and using copper for the wiring line for decrease the resistance R, the wiring delay ("Xgr"RC) can be reduced.
In order to decrease the wiring line resistance, it is also important to decrease an average wiring line length. Since the average wiring line length is inversely proportional to the number of wiring layers, a multiple-layer technique of the wiring layers is important. For this purpose, a damascene wiring structure technique and a chemical mechanical polishing (CMP) technique become essential which can attain the multiple-layer structure without involving concave and convex portions on the surface of a lower layer.
The CMP polishing is a step for precisely polishing a surface by using abrasive material in a process for manufacturing a semiconductor device. The CMP polishing precisely flattens an upper portion of a lower layer so as not to form any concave and convex portions on an upper layer. The manufacturing step is the very fine step. Thus, the high technique is required for the abrasive material, a polishing condition, a polishing apparatus, a rinsing method and the like.
The problems in the CMP of the conventional technique will be described below. The conventional technique will be described below with reference to FIG. 1. FIG. 1 is a diagram showing a step of rinsing after a CMP process is ended. FIG. 1 shows a wafer 101, pure water 102, a pure water nozzle 104, a rinse solution 103 and a rinse solution nozzle 105. Here, FIG. 1 shows a step of rinsing the back side of the wafer 101, in which the rinsing of the front side of the wafer 101 is ended after an unnecessary portion of a wiring film is CMP-polished.
On the wafer 101 are formed semiconductor devices such as semiconductor element, interlayer insulating films, damascene wiring lines and the like.
The pure water 102 is of a super high purity used to manufacture a semiconductor. The pure water 102 has a function of covering the front surface of the wafer 101 and thereby protecting impurities and the rinse solution 103 from going from back side to the front side.
The pure water nozzle 104 is provided to discharge the pure water 102 onto the front surface of the wafer 101.
The rinse solution 103 is used to remove abrasive residuals and contaminants which go onto the back side through the CMP polishing operation on the front side of the wafer 101.
The rinse solution nozzle 105 is provided to discharge the rinse solution 103 onto the back side of the wafer 101.
The front surface of the wafer 101 is rinsed after the formation of the copper damascene wiring line by the CMP polishing operation. After that, as shown in FIG. 1, the back side of the wafer 101 is rinsed by the rinse solution 103. At this time, the pure water 102 is discharged onto the front surface of the wafer 101 so that the contaminants on the back side do not go onto the side of the front surface.
The states of the damascene wiring line at this time will be described with reference to FIGS. 2A and 2B.
FIGS. 2A and 2B are cross sectional views showing the damascene wiring lines of the wafer 101. FIGS. 2A and 2B show a substrate 111, an insulating film 112, a barrier film 113, a wiring film 114 and a wiring line groove 115.
The substrate 111 is a semiconductor substrate on which semiconductor elements, (interlayer) insulating films, damascene wiring lines and the like are formed. The substrate 111 may be a semiconductor substrate formed of silicon, or a semiconductor substrate on which an insulating film formed of silicon dioxide and silicon nitride is formed.
The insulating film 112 is formed using an organic material such as a polymer of a hydrocarbon system or using an inorganic material such as silicon dioxide.
The barrier film 113 is a thin metal film. The barrier film 113 protects the interlayer insulating film 112 from being exposed to plasma, and also protects the wiring line film 114 from being diffused into the insulating film 112. The barrier film 113 is formed of titanium nitride, tantalum and the like.
The wiring line film 114 is formed of a metal with a low specific resistance. The wiring line film 114 is formed in a wiring line groove in the insulating film, and functions as the damascene wiring line. For example, the wiring line film 114 is formed of copper.
In FIG. 2A, the side of the front surface of the substrate 111 is rinsed after the damascene wiring line is formed in the wiring line groove 115 through the CMP polishing operation. After that, the back side of the substrate 111 is rinsed by the rinse solution 103 as shown in FIG. 1. When the back side is rinsed, the pure water 102 is sent onto the front side. The pure water 102 is sent in order to protect the rinse solution 103 for rinsing the back side from going onto the front surface. Next, FIG. 2B shows a cross sectional view when the back side rinsing is ended. In FIG. 2B, it is known that side slits are formed on the boundary between the wiring line film 114 and the barrier film 113.
In this way, the side slits occurs irrespectively of the stage at which the rinsing of the surface is ended after the completion of the CMP polishing operation. This is because the wiring line film 114 of copper is etched with the CMP polishing solution slightly remaining on the front surface and the pure water 102. Also, although being not shown, there may be a possibility that a pit is induced on the front surface through the etching.
Consequently, not only a sectional area of the wiring line is reduced, but also a location dependency occurs. That is, concave and convex portions are formed, which may result in a disturbance in a step coverage of an interlayer insulating film.
FIG. 3 is a view showing a different process of a rinsing after the CMP process is ended. FIG. 3 shows a wafer 101, pure water 102, a pure water nozzle 104, a rinse solution 103, a rinse solution nozzle 105, an end portion rinse solution 106 and an end portion nozzle 107. Here, FIG. 3 shows the process in which after an unnecessary portion of a wiring line film is polished through the CMP polishing operation, the rinsing on the front surface of the wafer 101 is ended, and the rinsing of the back side thereof and the removal of metal components of a surface edge are carried out at the same time.
The end portion rinse solution 106 is used for rinsing and removing the metal portion on the edge of the surface.
The end portion nozzle 107 is provided to supply the end portion rinse solution 106.
The other structures from the wafer 101 to the rinse solution nozzle 105 are as mentioned above. Thus, their description is omitted.
Also, in this case, the phenomenon shown in FIGS. 2A and 2B is brought about similarly to the above-mentioned case. The side slit is induced on the boundary of the barrier film of the damascene wiring line. Thus, it is difficult to effectively decrease the wiring line resistance. There may be a problem even in the step coverage of the interlayer insulating film.
In conjunction with to the above-mentioned description, Japanese Laid Open Patent Application (JP-A, 2001-89747) discloses a polishing composition and a polishing method. In this reference, a composition containing a benzotriazole derivative is used as the polishing composition when the CMP polishing operation is carried out. The copper CMP polishing operation is carried out by using the composition containing the benzotriazole derivative. Consequently, a protection film is formed on a copper surface, and the corrosion after the polishing operation is protected. In addition, a copper film polishing rate is suppressed.
Also, Japanese Laid Open Patent Application (JP-A-P2000-315666A) discloses a method of manufacturing a semiconductor integrated circuit device. In this reference, a polishing solution containing anticorrosive is used as polishing solution when the CMP polishing operation is carried out. The anticorrosive is medicine for forming a corrosive resistant protection film on a metal surface and thereby suppressing the progress of the polishing through the CMP polishing operation. Here, benzotriazole is used. Then, while a copper CMP polishing operation is carried out, the protection film is formed on the copper surface. Consequently, the corrosion after the polishing operation is protected. In addition, the copper film polishing rate is suppressed.
Japanese Laid Open Patent Application (JP-A-P2000-12543A) discloses a method of manufacturing a semiconductor integrated circuit device. In this reference, a slurry containing benzotriazole is used as a polish slurry when the CMP polishing operation is carried out. The usage of the slurry containing benzotriazole enables the polishing operation while the surface of a copper film is protected. Thus, it is possible to polish the copper film in which the corrosion of the copper film and the dishing are suppressed without any large reduction in a throughput.
Japanese Laid Open Patent Application (JP-A-Heisei 8-83780) discloses an abrasive material and a polishing method. In this reference, an abrasive material containing benzotriazole is used as the abrasive material when the CMP polishing operation is carried out. The usage of the abrasive material containing benzotriazole protects the surface of a copper film, and suppresses an isotropic chemical and mechanical polishing operation. Thus, only a convex surface of the polished film is removed by the mechanical polishing operation. Hence, it is possible to carry out the polishing operation in which the dishing is little.
Japanese Laid Open Patent Application (JP-A-Heisei, 8-64594) discloses a method of forming a wiring line. In this reference, abrasive particle solution containing benzotriazole is used as abrasive particle solution when the CMP polishing operation carried out. The usage of the abrasive material containing benzotriazole enables the protection of the surface of a copper film and the protection of the generation of the corrosion. Thus, it is possible to protect the surface corrosion during the formation of a metal wiring line during the polishing operation and after the formation, and thereby possible to protect the deterioration in a quality.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-315331) discloses a method of manufacturing a semiconductor device and a rinsing apparatus. In this reference, a copper wiring line is rinsed by using a water solution containing benzotriazole after the formation of the copper wiring line. The usage of the water solution containing benzotriazole enables a protection film (Cu-BTA) to be formed on the surface of the copper film, and thereby possible to protect the corrosion of the copper wiring.
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device, which can reduce damage to a damascene wiring line surface in a wet process to a wafer on which a damascene wiring line is formed.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can protect a damascene wiring line surface in rinsing the back side of a wafer on which the damascene wiring line is formed.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device, which can protect a damascene wiring line surface, in removing a metal on a surface edge of a wafer on which the damascene wiring line is formed.
It is another object of the present invention to provide a method of manufacturing a semiconductor device, which can stabilize a wiring line resistance and reduce a wiring delay.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can improve a wiring reliability without any decrease in a throughput.
In an aspect of the present invention, a method of manufacturing a semiconductor device is achieved by (a) forming an insulating film on a semiconductor substrate, by (b) forming a wiring line groove in the insulating film, by (c) forming a conductive film to fill the wiring line groove and to cover the insulating film, by (d) removing the conductive film using a CMP polishing method until the insulating film is exposed, to complete a wiring line, by (e) rinsing a front side of the semiconductor substrate on which the wiring line is formed, and by (f) rinsing a back side of the semiconductor substrate while supplying to the front side of the semiconductor substrate, a protection solution for forming a protection film in an exposed surface of the wiring line.
It is desirable that the conductive film is copper.
Also, it is desirable that the protection solution contains benzotriazole or benzotriazole derivative. The concentration of benzotriazole or benzotriazole derivative in the protection solution is desirably in a range of 0.01 to 0.1 wt %.
In another aspect of the present invention, a method of manufacturing a semiconductor device is achieved by (a) forming an insulating film on a semiconductor substrate, by (b) forming a wiring line groove in the insulating film, by (c) forming a first conductive film to cover an inner wall surface of the wiring line groove and the insulating film, by (d) forming a second conductive film to fill the wiring line groove and to cover the first conductive film, by (e) removing the first and second conductive films using a CMP polishing method until the insulating film is exposed, to complete a wiring line, by (f) rinsing a front side of the semiconductor substrate, on which the wiring line is formed, and by (g) rinsing a back side of the semiconductor substrate while supplying to the front side of the semiconductor substrate, a protection solution for forming a protection film in an exposed surface of the wiring line.
It is desirable that the conductive film is copper.
Also, it is desirable that the protection solution contains benzotriazole or benzotriazole derivative. The concentration of benzotriazole or benzotriazole derivative in the protection solution is desirably in a range of 0.01 to 0.1 wt %.
In another aspect of the present invention, a method of manufacturing a semiconductor device is achieved by (a) forming a first damascene wiring line above a semiconductor substrate using a conductive film, by (b) forming an upper insulating film on the damascene wiring line, by (c) forming a via-hole to pass through the upper insulating film to the first damascene wiring line, by (d) forming a second damascene wiring line in the via-hole, and by (e) rinsing a front side of the semiconductor substrate with a protection solution for protecting an exposed surface of the second damascene wiring line.
It is desirable that the conductive film is copper.
Also, it is desirable that the protection solution contains benzotriazole or benzotriazole derivative. The concentration of benzotriazole or benzotriazole derivative in the protection solution is desirably in a range of 0.01 to 0.1 wt %.
In another aspect of the present invention, a method of manufacturing a semiconductor device is achieved by (a) forming a damascene wiring line above a semiconductor substrate using a conductive film, by (b) rinsing a front side of the semiconductor substrate on which the damascene wiring line is formed, and by (c) rinsing a back side of the semiconductor substrate while rising the front side of the semiconductor substrate with a protection solution for protecting an exposed surface of the damascene wiring line.